Pick the appropriate settings for the cache organization you are interested in, then click on "configure".
Fill in an address (in decimal), click on either read or write, then hit return (while in the address box) and see what happens in the cache. You can do this repeatedly to see the effect of a series of CPU reads and writes.
The address is split into tag, index and position, and the result of the access is displayed. The affected cache line is shown in green. Valid blocks are light gray, invalid ones are dark gray. LRU points to the least recently used line in a set (only for the set-associative organization).
Note that this cache simulation ignores write misses and updates on write hits for a write-through cache. Other options will be added in a future version.
Note also that this cache simulation does not implement "dirty" bits for a write-back cache. Hence all blocks are written back whether they are dirty or not. This will be fixed in a future version.