CS3421, Fall 2008

The Problem

Your task is to construct part of the implementation of the CPU described below.

The CPU

Memory is 256 16-bit words and is word (not byte) addressed. There are four 16-bit registers ($0-$3), with $0 always having the value 0 (even if an instruction tries to change it). The intial values of the registers are: $1 = 1, $2 = 2, $3 = 3. All instructions are 16 bits, in one of two formats:

R-format

First (leftmost) 4 bits = op (the op code)
Next 2 bits = rs
Next 2 bits = rt
Next 2 bits = rd
Remaining 6 bits = unused

I-format

First (leftmost) 4 bits = op (the op code)
Next 2 bits = rs
Next 2 bits = rt
Remaining 8 bits = imm (immediate value - signed)

In the load and store instruction descriptions below, "EA" refers to the effective address, computed by adding the contents of the rs register and the sign extended immediate value in the instruction. The instructions are:

• halt
  Opcode = 0 or 14 or 15
  Stop execution (i.e., terminate the fetch/execute cycle).

• load rt,imm(rs)
  Opcode = 1
  rt = c(M[EA])

• store rt,imm(rs)
  Opcode = 2
  M[EA] = c(rt)

• add rd,rs,rt
  Opcode = 3
  rd = c(rs) + c(rt)

• sub rd,rs,rt
  Opcode = 4
  rd = c(rs) - c(rt)

• and rd,rs,rt
  Opcode = 5
  rd = c(rs) & c(rt)

• or rd,rs,rt
  Opcode = 6
  rd = c(rs) | c(rt)

• not rd,rs
  Opcode = 7
  rd = ! c(rs)

• sllr rd,rs,rt
  Opcode = 8
  rd = c(rs) shifted left (0 fill) by c(rt) bits

• srlr rd,rs,rt
  Opcode = 9
  rd = c(rs) shifted right (0 fill) by c(rt) bits

• addi rt,imm(rs)
  Opcode = 10
  rt = c(rs) + imm (sign extended)

• beq rs,rt,imm
  Opcode = 11
  if c(rs) == c(rt) then PC = imm

• blt rs,rt,imm
  Opcode = 11
  if c(rs) < c(rt) then PC = imm

• beq rs,rt,imm
  Opcode = 11
  if c(rs) <= c(rt) then PC = imm

The Partial CPU

For this lab you will implement the execute part of the fetch/execute cycle. You will need the four registers ($0-$3), a partial ALU, memory, and associated circuitry to make the instructions store, add and sllr finish in ONE cycle.

The encoded instruction will be found in the IR register. Your circuitry decodes the instruction in the IR and does just the execute part of its execution. You will not fetch the instruction, increment the PC, etc. The next lab assignment will add this functionality, along with the remaining instructions, in a multi-cycle implementation.

Getting Started

Copy the file CPU.jls from /classes/cs3421/common/lab5 and modify it to implement the CPU described above.

Circuit Restrictions

You must have a memory element in which the program being simulated is stored. It MUST be named "MEMORY" (all upper case). It MUST have an access time of 2000. It CANNOT be in a subcircuit. The CPU.jls file already has this element - don't delete it. You MUST have registers "R1", "R2" and "R3". They CANNOT be in a subcircuit. The CPU.jls file already has these elements - don't delete them. You MUST have an instruction register called "IR". It cannot be in a subcircuit. The CPU.jls file already has this element - don't delete it.

Use "named wires" with nice names to avoid long wires in the diagram. Feel free to define subcircuits as you see fit to make your circuit easier to understand (except don't put the items above in any subcircuits).

Propogation Delay and Cycle Time

Don't worry about minimizing propagation delay in order to make the cycle time as small as possible. I'm more interested in getting a correctly working slow machine than a fast machine that doesn't work. However do try to set the clock cycle time reasonably small given the circuitry you have. Do not change the propagation delays of any elements except DELAY elements.

Testing

Tools

The following tool is in /classes/cs3421/common/lab5.

• A simple assembler that reads an assembly language program file and creates a memory file. To run it, create a file containing an assembly language instruction (MARS syntax but lab5 instructions), then type:

  java  Asm  asmfile  memoryfile
  

  where asmfile is your assembly language program file name and memoryfile is the name of the memory file you want to generate. The memory file will have the encoding of the instruction you write in the assembly language file.

Submitting

Before you submit, make sure you have your name (and your partner's name if you have one) on your circuit.

Do not change the propagation delays of any elements except DELAY elements.

Also, make sure your memory element is called "MEMORY", your registers are called "R1", "R2" and "R3", and your instruction register is called "IR", and that none are in any subcircuits. If you don't you will get 0 on this assignment.

Use the submit command to electronically submit your "CPU.jls" file to "cs3421", assignment "lab5" by the due date.

You must submit your file by the due date/time in order to receive credit.