CS3421 Problem Set 13

Cache

  1. Consider a 64K direct-mapped cache with a 16 byte blocksize. Show how a 32-bit address is partitioned to access the cache.

  2. Consider a 3-way set-associative write-through cache with an 8 byte blocksize, 128 sets, and random replacement. Assume a 32-bit address. How big is the cache (in bytes)? How many bits total are there in the cache (i.e. for data, tags, etc.).

  3. Consider the design of a write-through cache. What options does a cache designer have for what to do when the CPU does a write and the cache has a copy of the block being written to?

  4. Suppose the blocksize of a cache is greater than than the wordsize read/written by the CPU. What must be done in a write-back cache with dirty bits when the CPU does a write and the cache does not have a copy of the block containing that word?

  5. Consider a 32 byte direct-mapped write-through cache with 8 byte blocks. Assume the cache updates on write hits and ignores write misses. Complete the table below for a sequence of memory references (occuring from left to right).

    address 00 16 48 08 56 16 08 56 32 00 60
    read/write r r r r r r r w w r r
    line# 0 2                  
    tag 0 0                  
    hit/miss miss                    

  6. Redo the problem above except assume the cache invalidates on a write hit.

    address 00 16 48 08 56 16 08 56 32 00 60
    read/write r r r r r r r w w r r
    line# 0 2                  
    tag 0 0                  
    hit/miss miss                    

  7. Consider a 128 byte 2-way set associative write-back cache with 16 byte blocks. Assume LRU replacement and that dirty bits are used to avoid writing back clean blocks. Complete the table below for a sequence of memory references (occuring from left to right).

    address 064 032 064 000 112 064 128 048 240 000
    read/write r r r r w w r r r w
    set# 0 2                
    tag 1 0                
    hit/miss miss                  
    write back? no