CS3421 Problem Set 9

Multi-Cycle MIPS Implementation

  1. Suppose it takes memory 100 nsec to read or write a word, the ALU and adders take 4 nsec, the register file can be read in 1 nsec, the PC, IR, A, B, ALUout, etc. can be read in 0.2 nsec, and all multiplexors take 0.1 nsec. Assume everything else takes 0 time (control, shift, sign extend, wires, etc.).

    What is the cycle time of the multicycle implementation?

  2. Assume that the cycle time of the multicycle implementation is 5 nsec. What is the average number of nsec required to execute an instruction if the instructions occur with the following frequency?

    instruction frequency
    R-type 25%
    lw 35%
    sw 15%
    beq 20%
    j 5%

  3. Modify the control state diagram so that it can handle the "addi" instruction. No datapath changes are needed.

  4. Modify the control state diagram so that it can handle the "jr" instruction. One minor change (an extra connection) to the datapath must be made - just describe it. Look carefully at the encoding of the "jr" instruction on page A-64 of the book.

  5. Modify the control state diagram and datapath so that it can handle the "jal" instruction. Hint - the datapath change is pretty simple (two modified multiplexors and a new connection).