CS3421 Problem Set 6

Sequential Circuits

  1. Why are edge triggered flip-flops preferred over level triggered latches in circuits where the input of a register can depend on the output of that same register?

  2. Complete the timing diagram below for the basic master/slave latch arrangement as shown in the book (negative edge triggered). 
      1|
QS |
  0|-
   |
   |
  1|
QM |
  0|-
   |
   |
  1| +----+  +-------+ +--+      +--+                 +----+ +-------
D  | |    |  |       | |  |      |  |                 |    | |
  0|-+    +--+       +-+  +------+  +-----------------+    +-+
   |
   |
  1|    +----------+          +----------+          +----------+
C  |    |          |          |          |          |          |
  0|----+          +----------+          +----------+          +-----
   +------------------------------------------------------------------------