make predefines a number of common commands as macros. For example, the macro ${CC} is usually defined to be the system C compiler, while ${LD} is defined to be the system linker. Therefore, if you have the following dependency line and command line:
It is usually equivalent to the following:myprog : main.c ${CC} -o myprog main.c
myprog : main.c cc -o myprog main.c
If your C compiler is not an ANSI C compiler, using macro ${CC} to compile an ANSI C program could generate a lot of error messages. To use gcc, you can redefine the CC macro as follows:
This will use gcc to compile the source program main.c producing an executable myprog.CC = gcc -ansi myprog : main.c ${CC} -o myprog main.c