Macros

Description file entries of the form

NAME = text string

are macro definitions. This line defines NAME to be the text string. Subsequent references to

${NAME}

$(NAME)

are interpreted as

text string

The following are some valid macro definitions:

LIBS = -lX11 -lm
OBJS = a.o b.o u.o some_thing.o
ARGUMENTS = "0 12 ABC"
CC   = gcc
DEBUG_FLAGS =
result = /usr/local/bin

Six macros are defined: LIBS, OBJS, ARGUMENTS, CC, DEBUG_FLAGS and result.

A macro definition is a line containing an equal sign (=). When make encounters a name that appears to the left of the equal sign, that name is replaced by the contents to the right of the equal sign. It is not necessary to delimit the text string with double quote (") or single quote ('). If they are used, they become part of the text string. For example, if ARGUMENTS is used in your makefile, it will be replace by "0 12 ABC".

If the text string to the right of the equal sign is too long (longer than a line), a back slash (\) can be used as the last character of that line, indicating that the next line is a continuation line. Here is an example:

LONG_LINE = -o myprog a.o openfile.o display_result.o \
             main_program.o plot_diagram.o \
             signal_handling.o \
            -lX11 -lm

make replaces any back slash by a blank and concatenates all continuation lines, yielding a long text string.

To ensure that make can distinguish a macro definition from a dependency line or a command line, no colons or tabs are permitted before the equal sign.

By convention, macro names are in uppercase. But, you can use any combination you want: uppercase and lowercase letters, digits, and underlines. You might also use some other punctuation characters; however, you should use them with care, since there is no guarantee that make will handle it correctly.

When you refer to a macro, as indicated earlier, you could enclose the name with ${} or $(). However, if the name has only one character, {} and () can be omitted. For example, if we have the following definition:

C = gcc

we can refer to gcc with $C, ${C}, or $(C).

Macros can use previously defined macros too. For example, if we have the following definitions:

OBJ_FILE_EXTENSION = .OBJ
EXE_FILE_EXTENSION = .EXE
EXECUTABLE         = myprog${EXE_FILE_EXTENSION}
OBJECT_FILE        = myprog${OBJ_FILE_EXTENSION}

references to EXECUTABLE and OBJECT_EXTENSION yield myprog.EXE and myprog.OBJ, respectively.

To the right of the equal sign, there could be no text string. In this case, the text string is considered to be a null string. DEBUG_FLAGS defined earlier is an example. If macros OBJ_FILE_EXTENSION and EXE_FILE_EXTENSION are replaced by the following definitions:

OBJ_FILE_EXTENSION = .o
EXE_FILE_EXTENSION =
EXECUTABLE         = myprog${EXE_FILE_EXTENSION}
OBJECT_FILE        = myprog${OBJ_FILE_EXTENSION}

references to EXECUTABLE and OBJECT_FILE yield myprog and myprog.o, respectively.